1. Field of the Invention
The present invention relates generally to semiconductor device fabrication, and more specifically to a system and method for discovering unknown problematic circuit patterns in chip design layout for semiconductor device manufacturing.
2. Description of Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Semiconductor devices are manufactured by fabricating many layers of circuit patterns on wafers to form a massive number of transistors for integration as complicated circuits. In the manufacturing flow of semiconductor devices, lithographic process (LP) is responsible for transferring circuit patterns created by circuit designers onto wafers.
Photomasks/reticles with opaque and clear patterns according to the circuit patterns are used for patterning device layers on wafers. Distortion of the patterns can result from the effect of the neighboring patterns on the photomask and optical diffraction, photoresist development and etching, chemical-mechanical polishing (CMP) on adjacent layers of the wafer, and geometric and overlaying relationships between patterns of adjacent layers fabricated on the wafer. As the component density of the integrated circuits (ICs) has increased the complexity of the IC patterns and layouts, distortion of the patterns often results in systematic defects that fail the device fabricated on the wafer or critical dimension (CD) errors that degrade the device performance.
FIG. 1 shows a typical flow in initial setup and on-going tune-up for optimizing the lithography process of manufacturing semiconductor devices. Circuit patterns for manufacturing the photomask of a device layer is described in a design data file generated by the circuit designer shown in block 101 that contains design data in GDS or OASIS format. The design data may be random layout circuit patterns generated from a random layout generator (RLG) or product qualification vehicle (PQV) from vendors or pilot customers. Block 102 shows optical proximity correction (OPC) creation that generates the required OPC by using the OPC model and recipe from block 103. After OPC creation, block 102 also performs OPC verification and lithographic process check (LPC) verification based on models of OPC and design for manufacturing (DFM).
OPC and LPC verification also predicts potential yield limiting hot spots caused by specific layout and patterns. As shown in block 104, wafers manufactured by the lithography process using the OPC photomask are examined by either optical or e-beam inspection and metrology tool to detect defects and measure critical dimensions in the hot spots. Inspection and metrology data of the predicted hot spots are fed back to block 103 to tune the models and recipes of OPC and DFM. In general, it is not easy to achieve perfect OPC/DFM models/recipes because the patterning errors come from various proximity and underneath effects including optical, chemical, etching, CMP and other processes as well as photomask/reticle errors. Even worse, some effects are short range and some are long range.
OPC is effective in achieving linewidth control if optical conditions during lithography match the simulated optical conditions used to arrive at the OPC solution. Defocus and exposure dose variations result in linewidth variation even after OPC. Focus variation during lithography is caused by changes in resist thickness, wafer topography and relative distance between wafer plane and the lens system. The dose variation typically comes from the scanner or from the illumination in the optical lithography system. Depth of focus and exposure latitude define the process window of a lithography system. Latest advances in process window aware OPC guarantee acceptable lithography quality but linewidth still varies within the process window. Linewidth variation has a direct impact on timing and leakage of designs.
Lithographic process simulation is typically used to simulate the circuit patterns and predict hot spots that are likely to cause pattern distortion. OPC and LPC are important techniques commonly used for correcting the pattern distortion. CMP simulation may also be performed on the circuit layout to determine hot spots. Alternatively, physical failure analysis (PFA) may be performed on the devices to identify hot spots. Process monitoring by sampling and inspecting wafers using the predicted or identified hot spots is necessary to ensure that systematic defects are identified and eliminated for manufacturing the semiconductor devices with high yield.
One approach commonly used in process monitoring is to collect scanning electron microscopic (SEM) images from a significant number of hot spots by sampling dies and wafers in the manufacturing flow. The hot spots may be predicted by LPC, CMP and other experience and a priori knowledge, or identified by PFA. Ideally, the more predicted hot spots, the less chance of missing critical defects. In practice, however, the number of hot spots used in process monitoring cannot overload the wafer inspectors and many of the predicted hot spots may also turn out to be non-systematic or non-critical because of modelling errors. How to predict the hot spots with most accuracy and good thoroughness has been a big challenge to the semiconductor manufacturers.
There is another drawback in the existing approaches to predicting the hot spots based on LP or CMP simulation of the chip design layout. Because the hot spots are predicted by applying LP or CMP model on the known chip design layout, the circuit patterns predicted as hot spots are limited within the available circuit patterns in the known chip design layout. A catastrophic systematic defect may occur in a revision of the chip design that includes new circuit patterns not covered by the hot spots. In addition, a well-qualified process line in the semiconductor fab may still run the risk of missing yield limiting defects when the semiconductor device of a new chip design is fabricated.